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UM10495 tda5051a lighting master-s lave demo board om13314 rev. 2 ? 11 may 2012 user manual document information info content keywords tda5051a, lpc1114, pcf8883, zero crossing and uart style synchronization, lighting demo abstract this document is a user manual for the tda5051a power line modem (plm) master-slave lighting controller demo om13314.
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 2 of 43 contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 revision history rev date description v.2 20120511 user manual; second release. ? figure 4 ? schematic for 4 pcf8883 capacitive proximity sensor switch ? updated (to improve readability) ? figure 24 ? tda5051a lighting demo board schematic ? updated (to improve readability) v.1 20110816 user manual; initial release.
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 3 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 1. introduction the tda5051a lighting control demo consists of a master controller and a slave lighting controller. the master controller uses the high-bay board, which consists of the lpc1114 microcontroller, the tda5051a plm ic, and power management circuitry. an ac-dc converter is used to provide +13 v dc supply voltage. the master employs 4 pcf8883 capacitive proximity switches to provide on /off, dim up, dim down, and select outputs of the remote lighting slave controller. the slav e controller consists of the high-bay board, an ac-dc converter to provide +13 v supply voltage, and an led array. both the master and the slave are housed in a plas tic box with 110 v ac power cords. fig 1. tda5051a master lighting controller fig 2. tda5051aslave lighting controller 002aag521 002aag522
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 4 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 2. plm demo board the tda5051a lighting demo board is designed to let customers evaluate the tda5051a in a realistic application. the tda5051a lighting demo board schematic is found in section 12 ? appendix b ? tda5051a lighting demo board schematic ? . the demo board includes a the tda5051a, an lpc 1114 microcontroller, a pca9632 i 2 c-bus to pwm converter, and software containing some pr e-defined functions to brighten and dim the four available led outputs from the pca9632. the parameters used by these functions can be easily changed by changing a configuration header file with parameter values used by the pre-defined functions. to furt her customize the application, the driver functions used in the demo firmware can be easily modified. 2.1 power line communications the tda5051a is an ask modem chip design ed for power line communications. in this application, the carrier frequency is 125 khz. however, the frequency can be changed with the specified range by ch anging the frequency of the crystal or clock input. the tda5051a consists of an agc amplifier and adc on the front with digital band-pass filtering and demodulation of the received signal. it also contains a lookup rom and dac to provide the proper wave shape and envelope for transmitted data. the internal amplifier then drives an external network to couple the transmit data onto the ac lines. 2.2 demo application overview the tda5051a demo board is designed for easy setup and ease of operation. the demo functions are executed by pressing one of fo ur control buttons located externally to the demo board. tda5051a demo functions su pported by the demo board and firmware include the following: off/on ? sends an on/off command to the slave via the plm dim up ? sends a dim up command to the slave via the plm dim down ? sends a dim down command to the slave via the plm select ? rotates the selected ch annel from the following: ? group ? pwm0 ? pwm1 ? pwm2 ? pwm3 some of the other features of the tda5051a demo board are: ? programmable device address (slave configuration) ? requires 12 v input, has onboard +5 v and +3.3 v regulators ? flexible re-programming, firmware updating ? swd ? rs-232
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 5 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 this document will also discuss the firmware required to implement the demos. one set of firmware was written utilizing the zero crossing of the ac line as a method to synchronize transmission. the other set of firmware was written to use a start bit/stop bit synchronization similar to a ua rt to allow transmission over dc lines that have no zero crossing information. 3. hardware requirements the hardware requirements for both firmware implementations are similar when using the ac line as transmission medium. due to th e synchronization diff erences of the two different firmware implementations, the uart style would not need the opto-coupler that is on the tda5051a demo board. consider ations for other implementations will be discussed in a later section. even though the same demo board is used for both the master and the slave, not all components are used in both configurations as discussed later in section 4 and section 5 . 3.1 master hardware configuration to implement the master the hex address switch sw1 is not needed. if sw1 is populated, set the switch to the ?0? position (all ?open?). this allows four exte rnal switches to be connected to the same pins on the microcontr oller as sw1 without generating a conflict. the external switches mate with the sv2 connector on the demo board. a dc power supply and connection to the ac line are also needed for the master. additional details can be found in section 4 . 3.2 slave configuration to implement the slave for the ssl demo, the tda5051a demo board, four leds with current limiting resistors, an ac line connection, and a dc power input are required to implement a plm slave for the ssl demo. the slave actions in response to received commands are discussed in section 5 . 4. master hardware descript ion ? tda5051a demo board in the master configuration, the tda5051 a demo board reads switch closures and generates commands that are transmitted by the tda5051a over the ac lines. the details of how the lpc1114 handles these tas ks will be discussed in the firmware portion of the users manual. 4.1 tda5051a demo board ? general the nxp tda5051a and the lpc1114 are the heart of the board with the tda5051a providing the modem interface to the power lines and the lpc1114 providing a high-performance programmable processor at low power and low cost. it handles all of the ?intelligent? functions of the board and manages the peripheral interfaces.
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 6 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 4.2 tda5051a demo board ? i/ o, master configuration the tda5051a demo board provides a number of switches and visual indicators to control and monitor the power line communications. the details on how these are used in the master configuration are discu ssed in the following sections. 4.2.1 onboard visual indicators ta b l e 1 shows the onboard leds and their func tion in the master configuration. [1] when pressing the external ?select? switch, the com led will blink to indicate which item is being selected as detailed in section 4.2.2 . 4.2.2 external switch interface the master configuration requires four extern al switches to be connected to header sv2. this may be implemented with a 4 pcf8883 capacitive proximit y sensor switch circuit shown in figure 4 . the connector pin assignments are shown in ta b l e 2 . fig 3. block diagram of master lighting controller 002aag470 ac-dc converter 13 v output zero cross +5 v power line modem tda5051a +5 v ldo 12 v to 220 v ac/dc +3.3 v supply zener/ pass jtag com_led blinks to indicate which led is selected normal operation: blinking hb_led at 1 second intervals; stops blinking with slave fault lpc1114 +3.3 v rx tx pd clk_out +3.3 v +5 v 4 pcf8883 capacitive proximity switches or push button switches on/off dim up dim down select outputs table 1. onboard leds and function led label led function control drive source notes hb_led processor heartbeat lpc1114 - pio3_2 blinks when operational com_led com status lpc1114 - pio3_4 blinks when ?select? is pressed [1]
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 7 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 (1) jp0 connects to pin 1 of sv2 header. (2) jp1 connects to pin 2 of sv2 header. (3) jp2 connects to pin 3 of sv2 header. (4) jp3 connects to pin 4 of sv2 header. (5) gnd (ground) connects to pin 5 of sv2 header. (6) v cc connects to +3.3 v supply. fig 4. schematic for 4 pcf8883 capacitive proximity sensor switch 019aac664 on/off dim up dim down output select 14 1 74ahc04 7 8 1 gnd jp3 1 jp14 1 jp10 1 1 1 jp2 jp1 jp0 1 1 jp1 jp13 c21 1 f gnd +3.3 v v cc r12 270 r13 270 led4 gnd 1 jp9 led3 r10 270 led2 1 jp12 r9 270 led1 gnd c1 1 f c9 39 pf gnd us1 18 1 jp8 v cc c2 1 f gnd c17 330 nf c16 27 pf gnd r1 51 k r5 5.1 k ps1 ps1 c3 1 f c10 8.2 pf gnd us2 18 1 jp7 v cc c4 1 f gnd c18 330 nf c15 27 pf gnd r2 51 k r6 5.1 k ps1 ps1 c5 1 f c11 8.2 pf gnd us3 18 1 jp6 v cc c6 1 f gnd c19 330 nf c14 27 pf gnd r3 51 k r7 5.1 k ps1 ps1 c7 1 f c12 18 pf gnd us4 18 1 jp5 v cc c8 1 f gnd c20 330 nf c13 27 pf gnd r4 51 k r8 5.1 k ps1 ps1
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 8 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 [1] rotates the selected channel from the followi ng and blinks the com_led when changed as noted below: group 1 com led long blink pwm0 1 com led short blink pwm1 2 com led short blinks pwm2 3 com led short blinks pwm3 4 com led short blinks 4.2.3 demo board connections ? master configuration a tda5051a demo board, four switches, an ac line connection, and a dc power input are required to implement a master for the ssl demo. the functions assigned to the switch inputs are discus sed in a later section. the interface connections to the tda5051a demo board are shown in figure 5 . table 2. sv2 header pin assignments header pin switch function signal destination notes 1 off/on lpc1343 - pio1_8 sends an on/off command 2 dim up lpc1343 - pio1_9 sends a dim up command 3 dim down lpc1343 - pio1_10 sends a dim down command 4 select lpc1343 - pio1_11 rotates the selected channel [1] 5 - ground fig 5. tda5051a demo board interface connections 002aag472 com_led ac line (+) dc power (?) debug interface rs-232 interface (isp) isp jumper external switches address switch (master set to 0) hb_led
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 9 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 5. tda5051a demo boar d ? slave configuration in the slave configuration, one of the tasks of the lpc1114 microcontroller is to detect when a command has been received over th e power lines and execute the command. in the demo firmware provided, the commands received over the power lines result in sending an i 2 c message to the pca9632 led pwm controller to control the output brightness of four externally connected leds. fig 6. block diagram of slave lighting controller 002aag473 ac-dc converter 13 v output zero cross +5 v power line modem tda5051a +5 v ldo 12 v to 220 v ac/dc +3.3 v supply zener/ pass jtag com_led blinks to indicate successful communications normal operation: blinking hb_led at 1 second intervals; stops blinking with slave fault lpc1114 +3.3 v rx tx pd clk_out +3.3 v +5 v i 2 c-bus temp and ambient light sensors pca9632 pwm0 to pwm3 0 v to 10 v boost mosfet 4 hb leds module address set switch
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 10 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 5.1 tda5051a demo board ? i/o, slave configuration the tda5051a demo board provides a number of switches and visual indicators to control and monitor the power line communications. the details on how these are used in the slave configuration are discussed in the following sections. 5.1.1 onboard visual indicators ? slave configuration ta b l e 3 shows the onboard leds and their f unction in the slave configuration. 5.1.2 external led interface the led outputs from the pca9629 can drive leds directly, up to a specified limit, or it can provide pwm controlled dimming for external high current led power supplies. in the demo application, an external array of four white, low power leds is driven from the pca9632. the leds are biased with current limiting resistors and an external connection to a power supply on the demo board (see the schematic in figure 7 ). the connection to the external leds is via header j501 on the tda5051a demo board with the pin assignments is given in ta b l e 4 . table 3. onboard leds, function in slave configuration led label led function control drive source notes hb_led processor heartbeat lpc1114 - pio3_2 blinks when operational com_led com status lpc1114 - pi o3_4 blinks when communicating table 4. pin assignments for external led connection via header j501 header pin function signal destination notes 1 pwm3 led3 via external cl resistor to +3.3 v 2 gnd supply gnd 3 pwm2 led2 via external cl resistor to +3.3 v 4 pwm1 led1 via external cl resistor to +3.3 v 5 pwm0 led0 via external cl resistor to +3.3 v x = connections to 3.3 v supply and header j501 on tda5051a demo board. fig 7. schematic for external array of four white leds 002aag474 r4 d3 led3 +3.3 v r3 d2 led2 r2 d1 led1 r1 d0 led0
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 11 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 5.1.3 demo board connections ? slave configuration fig 8. tda5051a demo board connections for slave configuration 002aag475 com_led ac line (+) dc power (?) debug interface rs-232 interface (isp) address switch (set to 1) hb_led external leds
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 12 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 6. protocol requirements the objective of this demo so ftware is to provide a protoc ol structure that defines the bit level frames and message frames to prov ide a number of capabilities including the following: ? source and destination addresses allowin g multiple masters and multiple slaves ? parity and checksum error detection and message re-transmission to increase reliability of communications ? sub-address to communicate with multiple channels within a fixture ? bidirectional communications to allow getting status or configuration information from slaves the message level protocol for implementations using zero crossing or start bit synchronization is the same, however the bit level frames are different as discussed in the next section. 6.1 bit frame protocol consideratio ns ? zero crossi ng synchronization by using the zero crossing of the ac signal to synchronize the bit frame, we can structure the protocol to avoid the peaks of the ac line where the noise is greatest and the line impedance is the lowest. most low power factor equipment dr aws the most current at the peaks. as a result, the line impedance may drop significantly when t he rectifier diodes in the equipment are conducting at the peaks of the ac line. this can affect the amount of signal coupled onto the ac line potentially causing errors. by having the bit frame start 1 ms after the peak of the ac sine wave and ending the bit frame 1 ms before the ac peak, the noisy, low-impedance portion of the ac line can be avoided, increasing the reliability of the communication s link. for received data, 16 sample clock is generated and five samples are taken in the middle of the bit time. the received state of the sampled bit is determined by the majori ty of the five samples taken. this helps reduce reception errors due to short noise spikes that may occu r at a sample time, but is averaged out over several samples. the bit frame for the zero crossing implementation will be detailed in section 7 . 6.2 bit frame protocol considerat ions ? start bi t (uart style) synchronization for some applications such as dc links (sol ar panels, dc power distribution), a zero crossing signal is not available. also, when coupling between different phases, the zero crossing time of the master is not coincident with the zero crossing of the slave. for these applications, firmware was develope d that uses a start bit to synchronize the reception of the data so a zero crossing is not required. after the start bit, a frame bit is needed to provide message level synchronization. the fr ame bit is then followed by eight data bits, a parity bit and a stop bit. in the same way as was done with the zero crossing firmware, a 16 receive clock is generated and five samples taken in the middle of the bit time. the received state of the sampled bit is determined by the majority of the five samples taken to increase noise immunity as no ted in the previous section.
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 13 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 7. protocol specification two sets of firmware were generated for the tda5051a demo board for the two different synchronization methods discussed in the previo us section. each set includes master and slave firmware. the following protocol spec ifications were generated based on the requirements listed in section 6 . 7.1 protocol specification ? zero crossing synchronization 7.1.1 bit level protocol ? zero crossing synchronization in transmitting over the ac lines, there is a region approximately 2 ms wide centered on the peaks of the ac sine wave where line disturbances have the greatest chance of corrupting the data transmission and receptio n. one of the line disturbances is due to added noise from any number of sources that are active during this time. with low power factor power supplies, the rectif iers only conduct at the peaks of the ac signal. this can result in lowering of the line impedance during this period. this can lower the amount of signal coupled on to the line by the master as well as reducing the amount of signal received by the slave. when synchronizing to the zero crossing, the bit level transmission frame can be offset from the detected zero cr ossing. the protocol then specifies 2 ms of dead time centered over the peaks of the ac line to avoid the ?disturbance region? of the ac line. at 60 hz, a half-cycle of the ac li ne is 8.33 ms in duration. avoiding the 2 ms disturbance region leaves 6.33 ms to transmit the bit frame. this does not leave enough time to transmit a byte of data (with framing and parity bi ts). as a result, the half-byte is transmitted every half-cycle. the start of the frame is offset from the zero crossing by about 5.16 ms (about 1 ms after the ac peak). th e format of the bit level frame is detailed in figure 9 . if the frame bit is 0, it indicates the following bits should contain a valid frame byte flagging the beginning of a message frame. when the frame bit is 1, the bits [0:3] during the first half cycle and bits [4:7] in the second half cycle should contain a valid frame byte. the value of the parity bit is then calculated including the frame bit and bits [0:3 ] or [4:7] depending on the half-cycle indicated by the cycle frame bit. if the frame bit is 1, and a frame byte has alread y been received, this indicates the following bits should contain a data byte or checksum byte depending on the position after the frame bit. the value of the parity bit is then calculated includi ng the frame bit and bits [0:3] or [4:7] depending on the half-cycle indicated by the cycle frame bit. if the cycle frame bit is ?0?, this indicates this frame corresponds to the first half-cycle of the transmitted data and contains data/frame bits [0:3]. if the cycle frame bit is ?1?, this indicates this frame corresponds to the second half-cycle of the transmitted data and contains data/frame bits [4:7]. the dead time allows time for the slave to process the current data transmitted as well as allowing the master and the slave to avoid transmitting during the peaks of the ac line. at 60 hz, the time of a half-cycle is 8.33 ms. pr oviding 2 ms of dead time leaves 6.33 ms to transmit 7 bits, resulting in a data rate of 1105 bit/s. fig 9. bit level frame format 002aag476 frame bit cycle frame bit bit 0/4 bit 1/5 bit 2/6 bit 3/7 parity bit dead time (2 ms)
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 14 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 7.1.2 message level protocol the message level protocol was designed to provide a number of features. the message structure has the ability work with multiple ma sters and multiple slave by having a master and slave address included in the frame. error handling is also included by providing a message checksum along with the frame by frame parity to detect erro rs. the message level protocol is detailed in figure 10 starting with the master transmit message frame. the start byte is a specific value for a mast er transmission and indicates the beginning of a message. the slave address is the destinati on and for lighting applicat ions is typically a lighting fixture. it could also potentially address a bridge device such as a plm/dali bridge, or plm/rs-232 bridge to allow communications between protocols. the master address is present to support multi mast ers. for example, for home lighting, there may be masters in every room. so, a slave could be pr ogrammed to only respond to the master in the room it is located in. it could also respond to br oadcast command to turn off or dim lights at certain hours, or when a residence is vacated for energy management. the sub address could be a specific light or color in the lighting fixture. or, in the case of a dali bridge device, this could be the dali address byte. the command byte tells the slave how to res pond. the proposed protocol uses similar command assignments as dali. in a dali bridge device, th is would be the dali command. if similar command assignments are used in the plm protocol, no command translation would be required in a dali bridge device. data byte1 / data byte 2 are available if the command indicates the slave should use the data that follows. depending on the specified command, the data bytes can be interpreted as two 8-bit values or one 16-bit value. in a plm/rs-232 bridge device, this number of bytes could be expanded to allow for more data bytes if needed. larger frames are not intended to be supported in the initial implementation for the lighting application. the checksum byte contains the two?s complem ent checksum of the previous seven bytes. the slave should sum the start byte and all remaining by tes including the checksum. if the result is ?0?, the frame has been received without a checksum error. fig 10. master transmit message frame 002aag477 start byte slave address master address sub address command byte data byte 1 data byte 2 checksum byte
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 15 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 the slave will respond to the master if the command is re ceived with a valid start byte. a completion code of ?0? indicates the mast er?s command was received with parity bits correct, the checksum correct, a valid start byte, and the correct number of bytes received. completion codes could be assigned to parity or checksum errors so statistics can be obtained for these if desired. other completion codes for special error conditions could also be defined if ne eded. if the master receives no response, the master will transmit the message up to three times (configurable) before aborting the attempt. the data bytes in the response frame could prov ide the ability to query the slave about its status, configuration, etc. even though the frame structure could support slave queries, the application code described here only implements basic communications and command functions to demonstrate capabilitie s while leaving enough flexibility to allow the user to enhance the code as needed for their own applications. 7.2 protocol specificat ion ? start bit (uart style) synchronization 7.2.1 bit level protocol ? start bit (uart style) synchronization there are applications where zero crossing synchronization is not feasible. this specification was developed and firmware was written to address those situations. a start bit transition and additional data samples are used to synchronize the reception of the data so a zero crossing is not required. after the start bit, a frame bit is used to provide message level synchronization. the frame bit is then followed by eight data bits, a parity bit and a stop bit. in the same way as was done with the zero crossing firmware, a 16 receive clock is generated and five samples are taken of all bit in the middle of the bit period. the received state of the sampled bi t is determined by the majority of the five samples taken to increase noise immunity as noted in the previous section. synchronization at the bit level is performed in the same manner as a uart. the idle state of the ?soft? plm uart rx and tx pins on the microcontroller is ?high?. since this matches the tda5051a idle state, we ca n directly connect the tx pin on the microcontroller to the data_in pin on the tda5051a. and, likewise, we can connect the ?soft? plm uart rx pin on the micro to the data_out pin on the tda5051a. so the ?high? and ?low? states re ferred to in the specification per tain to the logic levels of the interface between the microcont roller and the tda5051a. the bit level frame is shown in figure 12 . fig 11. slave receive message frame 002aag478 start byte master address slave address command byte completion code data byte 1 data byte 2 checksum byte
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 16 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 8. master firmware overview to implement the master application, three commands were defined and enumerated: dim up, dim down, and on/off. these commands are initiated by pressing one of three external switches or touch sensors (active low) that are connected to port pins p1_8, p1_9, p1_10 of the lpc1114 microcontroller. the fourth switch connected to p1_11 and will rotate through the differen t control channels available and set the sele cted channel number in the outgoing plm transmit frame. the details of the protocol and the command and response frame structure are discussed later. p1_8: off/on ? sends an on/off command to the slave via the plm p1_9: dim up ? sends a dim up command to the slave via the plm p1_10: dim down ? sends a dim down command to the slave via the plm p1_11: select ? rotates the selected channel from the following: ? group ? pwm0 ? pwm1 ? pwm2 ? pwm3 more details of how these commands are in terpreted will follow in the slave section ( section 9 ). the start bit is always low. this is used as synchronization as the stop bit and any idle time after the stop bit are defined to be high. as a result, there is always a high-to-low transition at the beginning of a bit frame to synchronize the reception of the rest of the bits in the bit frame. this means the master transmit and slave receive baud rates must be set equal to be able to sample the received signal at the correct times. in addition to using the ?high-to-low? transition to synchronize the receive sampling, the start bit is also sampled half a bit period after the ?high? to ?low? transition. this is to veri fy a valid start condition exists. if the frame bit is 0, it indicates the following bits should contain a valid frame byte flagging the beginning of a message frame. when the frame bit is 1, the bits [0:7] in the field should contain a valid frame byte. the value of the parity bit is then calculated including the frame bit and bits [0:7]. if the frame bit is 1, it indicates the following bits should contain a data byte or checksum byte depending on its position after the frame bit. the value of the parity bit is then calculated including bits [0:7]. the stop bit is always high, providing time for the slave to process the current data transmitted and to provide at least 1 bit period of idle stat e to facilitate detection of the next start bit. fig 12. bit level frame 002aag479 frame bit bit 0 bit 1 bit 2 bit 3 parity bit start bit bit 4 bit 5 bit 6 bit 7 stop bit
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 17 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 there are two led indicators on the tda5051a used by the master. the ?hb led? is for the heartbeat function to indicate that the microcontroller is functioning when blinking. the ?com led? indicates which of the functions is se lected when the select switch is activated by the following indications: one short blink ? pwm0 is selected two short blinks ? pwm1 is selected three short blinks ? pwm2 is selected four short blinks ? pwm3 is selected one long blink ? group is selected the master transmission contai ns a slave address to select which device will recognize its commands. since there are no additional inputs on the tda5051a demo board to set this address, it is ?hard coded? to be 0x01. 8.1 master firmware implementati on ? zero crossing synchronization the master firmware for the tda5051a ssl demo applicatio n contains a number of ?c? application modules combined with system and core code. the modules are described in section 8.1.1 through section 8.1.12 . 8.1.1 main_loop.c this module calls all the initialization code for all the other modules and provides the while (1) loop to test for application flags. the flags tested by the master include byte level and message level receive flags, transmit status, and transmit error flags. if the flag gets set, the test function will call applic ation function in th e related module. 8.1.2 16b_timer1.c timer 16b1 on the lpc1114 provides the receive sample timing and is set to interrupt at a rate 16 transmit data rate. the middle five samples of each bit time are used to determine the logic state of the received bit by state of a majority of the samples. the start of the sample time is determined by an offset from the zero crossing. 8.1.3 uart.c this was used as a debug channel during development. 8.1.4 io.c this configures the i/o of the lpc1114 includi ng setting the functions and direction of the i/o pins. the i/o interfacing with the zero cros sing opto couple generates an interrupt on both edges of the signal. the pulse width of the optocoupler output is measured to estimate the zero crossing as described later. this module also contains the functions to detect the closure of a command switch and take the appropriate action or sent the corresponding command to the slave. 8.1.5 command.c this was used for initial debug.
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 18 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 8.1.6 nvic.c this sets the priority and enables required interrupts in the nested vectored interrupt controller (nvic). the enable interrupts include timers 32b0, 32b1, 16b0, 16b1, and external interrupt eint0. 8.1.7 systick.c the systick timer provides the heartbeat and de lay function timing. the transmit time-out counter is also implemented using the systick interrupt. 8.1.8 32b_timer0.c the 32b0 timer provides the transmit timing for the master transmitter. this is a 1 clock synchronized by an offset from the zero crossi ng. this provides a timing reference for the output data. 8.1.9 plm_master.c this handles the message level communications for the plm master, providing synchronization, transmitting commands, receiving acknowledgements, and handling error conditions. this module also contains the external interrupt handle r that is active on both edges of the zero crossing opto-coupler. this is used to determine the estimated zero crossing using time r 32b1 as described in section 8.1.10 . 8.1.10 32b_timer1.c this is used to time the start of frame offset from the zero crossing. part of this involves timing the pulse width of the zero crossing pulse from the opto-coupler. since the opto-coupler output is symmetrical around th e actual zero crossing, the time from the second edge of opto-coupler pulse to the actual zero crossing can be estimated by dividing the pulse width by two. this is subtra cted from the number of counts required for the 5.16 ms offset and loaded into timer 32b1 to set the offset time from the second edge. the timer 32b1 interrupt th en sets the start time of the offset bit frame. 8.1.11 timer16b_0.c the master uses this as the debou nce timer for the switch inputs. 8.1.12 plm_uart.c this contains the routines that handle the bi t level synchronization and data transmission and reception. this uses the timing refere nces from the 16b1 and 32b2 timers to implement a soft uart specifically for the interfacing to the tda5051a.
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 19 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 8.2 master firmware implementa tion ? start bit (uart style) synchronization the master configuration for implementing the start bit synchronization method is the same as the zero crossing method at the high level. the switch commands and indicator actions are the same for the firmware implem entations of both synchronization methods. the differences discussed in the protocol se ction are detailed when discussing how the synchronization methods are handled in the individual firmware modules. the master firmware for the tda5051a ssl demo applicatio n contains a number of ?c? application modules combined with system and core code. the modules are described in section 8.2.1 through section 8.2.12 . 8.2.1 main_loop.c this module calls all the initialization code for all the other modules and provides the while (1) loop to test for application flags. the flags tested by the master include byte level and message level receive flags, transmit status flag to see if all bytes in message have been transmitted, and transm it error flag. if the flag ge ts set, the test function will call an application function in the related module to act. 8.2.2 16b_timer1.c timer 16b1 on the lpc1114 provides the receive sample timing and is set to interrupt at a rate 16 transmit data rate. the middle five samples of each bit time are used to determine the logic state of the received bit by state of a majority of the samples. the start of the sample time is determined by an offset from the zero crossing. 8.2.3 uart.c this is only used for debug. 8.2.4 io.c this configures the i/o of the lpc1114 includi ng setting the functions and direction of the i/o pins. this also configures the rx pin us ed by the plm uart as an external interrupt that detects the high-to-low tr ansition at the beginning of the start bit. this module also contains the functions to detect the closure of a command switch and take the appropriate action or sent the corresponding command to the slave. 8.2.5 command.c this is only used for debug. 8.2.6 nvic.c this sets the priority and enables required interrupts in the nested vectored interrupt controller (nvic). the enabled interrupts include timer 32b0, timer 16b1, and the external interrupt. 8.2.7 systick.c the systick timer provides the heartbeat and delay function timing. 8.2.8 32b_timer0.c the 32b0 timer provides the transmit timing for the master transmitter.
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 20 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 8.2.9 plm_master.c this handles the message level communications for the plm master, providing synchronization, transmitting commands, receiving acknowledgements, and handling error conditions. this module also contains t he external interrupt handler that detects the start bit for bit level synchronization. 8.2.10 32b_timer1.c this is used to time the start of frame offset from the zero crossing. part of this involves timing the pulse width of the zero crossing pulse from the opto-coupler. since the opto-coupler output is symmetrical around th e actual zero crossing, the time from the second edge of opto-coupler pulse to the actual zero crossing can be estimated by dividing the pulse width by two. this is subtra cted from the number of counts required for the 5.16 ms offset and loaded into timer 32b1 to set the offset time from the second edge. the timer 32b1 interrupt th en sets the start time of the offset bit frame. 8.2.11 timer16b_0.c the master uses this as the debounce timer for the control switch inputs. 8.2.12 plm_uart.c this contains the routines that handle the bi t level synchronization, data transmission, and reception. this uses the timing references fr om the 16b1 and 32b2 timers to implement a soft uart specifically for the interfacing to the tda5051a. 9. slave firmware description to implement the slave application, an on-board hex switch is used to set the slave address. this is connected to port pins p1_8, p1_9, p1_10, and p1_11. the address assigned to the hex switch is specified as follows: p1_8: 2^8 p1_9: 2^4 p1_10: 2^2 p1_11: 2^1 the sum of the addresses for the logic ?high? inputs results in the slave address recognized for commands. for exam ple, when the hex switch is set to ?1?, p1_11 will be ?high? and p1_8 ? p1_10 will be ?low?. remark: since the master hard codes a slave address of ?0x01?, make sure the hex switch on the slave is set to this address to be able to respond to master commands. there are two led indicators on the slave. the ?hb led? is for the heartbeat function to indicate that the microcontroller is functi oning. the ?com led? blinks when a valid frame byte has been received to indicate communications activity. the slave configuration for implementing the start bit synchronization method is the same as the zero crossing method at the high level. the command responses and indicator actions are the same for the firmware implem entations of both synchronization methods. the differences are detailed in the individ ual module sections when discussing how the different synchronization methods are handled.
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 21 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 9.1 slave firmware description ? zero crossing synchronization the slave firmware for the tda5051a ssl de mo application contains a number of ?c? application modules combined with system and core code. the modules are described in section 9.1.1 through section 9.1.14 . 9.1.1 main_loop.c this module calls all the initialization code for all the other modules and provides the while (1) loop to test for application flags. the flags tested by the master include byte level and message level receive flags, transmit status flag to see if all bytes in message have been transmitted, and transmit response flag . if the flag gets set, the test function will call an application function in the related module to act. 9.1.2 16b_timer1.c timer 16b1 on the lpc1114 provides the receive sample timing and is set to interrupt at a rate 16 transmit data rate. the middle five samples of each bit time are used to determine the logic state of the received bit by state of a majority of the samples. 9.1.3 uart.c this was used for initial debug. 9.1.4 io.c this configures the i/o of the lpc1114 includi ng setting the functions and direction of the i/o pins. the i/o interfacing with the zero crossing opto-coupler also generates an interrupt on both edges of the signal. this pulse width of the opto-coupler output is measured to estimate the zero crossing as described later. 9.1.5 command.c this is only used for debug. 9.1.6 nvic.c this sets the priority and enables required interrupts in the nested vectored interrupt controller (nvic). the enable interrupts include timers 32b0, 32b1, 16b0, 16b1, and external interrupt eint0. 9.1.7 systick.c the systick timer provides the heartbeat and delay function timing. 9.1.8 32b_timer0.c the 32b0 timer provides transmit timing allowing the slave to respond back to a master. 9.1.9 i2c.c this contains the driver code for the i 2 c-bus peripheral on the lpc1114. the i 2 c interface is used by the slave to communicate with the pca9632 i 2 c-bus to pwm led driver. the application specific code is contained in the ?i2c messages.c? module described in section 9.1.10 .
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 22 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 9.1.10 i2c messages.c this module contains the functions that in terpret the incoming commands and channel assignments and sends corresponding i 2 c messages to the pca9632. the pca9632 is initialized in the ?group dim mode? where a 190 hz fixed frequency ?group? signal is superimposed with the 6.25 khz individual brightness control signals pwm0, pwm1, pwm2, and pwm3. the ?select? function on th e master sets the outgoing channel number in the plm master transmit frame. this channel number is read by the slave to determine which register on the pca9632 is addressed when it sends out i 2 c commands. the corresponding registers on the pca9632 and a short description are shown in ta b l e 5 . this mode is useful to be able to set the br ightness ?mix? of the different outputs, then increasing or decreasing all outputs at th e same time while still maintaining the same ?mix?. refer to the pca9632 data sheet ( ref. 1 ) for more information. the brightness levels of both the grppwm and pwmx registers are initialized at a mid level of brightness. to get maximum duty cycle from the outputs, increase both group and individual levels via the master ?dim up? and ?dim down? and ?select?. the off/on command from the master results in the slave sending an i 2 c message to the pca9632 to enable or disable all or none of the ledx output drives via the ledout register on the pca9632. the actual levels sent to the grppwm and pwmx registers are incremented via functions that provide a simple piece- wise linear approximation of a logarithmic dimming curve. as the eye sensitivity is logarithmic, providing some approximation of this gives the dim up and dim down commands a more natural response. the dimming curve functions are located in the plm_slave module discussed in section 9.1.11 . 9.1.11 plm_slave.c this handles the message level communications for the plm slave, providing synchronization, rece iving commands, transmitting acknowledgements, and handling error conditions. the receiv ed ?dim up? and ?dim down? comma nds result in pwm values that are incremented or decremented through simple dimming curve functions contained in this module as discussed in the previous section. this module also contains the external interrupt handler that is active on both edges of the zero crossing opto-coupler. this is used to determine the estimated zero crossing using timer 32b1 as described in section 9.1.12 . 9.1.12 32b_timer1.c this is used to time the start of frame offset from the zero crossing in the same manner as the master. part of this involves timing the pu lse width of the zero crossing pulse from the opto-coupler. since the opto-coupler output is symmetrical around the actual zero crossing, the time from the second edge of opto-coupler pulse to the actual zero crossing can be estimated by dividing the pulse width by two. this is subtracted from the number of table 5. pca9632 corresponding registers register range of values description grppwm 0 to 15 this is used as a global brightness control allowing the led outputs to be dimmed with the same value pwm0 0 to 63 individual brightness control for pwm0 output pwm1 0 to 63 individual brightness control for pwm1 output pwm2 0 to 63 individual brightness control for pwm2 output pwm3 0 to 63 individual brightness control for pwm3 output
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 23 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 counts required for the 5.16 ms offset and loaded into timer 32b1 to set the offset time from the second edge. the timer 32b1 interrupt then sets the start time of the offset bit frame. 9.1.13 timer16b_0.c the master uses this as the debou nce timer for the switch inputs. 9.1.14 plm_uart.c this contains the routines that handle the bi t level synchronization, data transmission, and reception. this uses the timing references fr om the 16b1 and 32b2 timers to implement a soft uart specifically for the interfacing to the tda5051a. 9.2 slave firmware description ? star t bit (uart style) synchronization the slave firmware for the tda5051a ssl de mo application contains a number of ?c? application modules combined with system and core code. the modules implemented for start bit synchronization are described in section 9.2.1 through section 9.2.12 . 9.2.1 main_loop.c this module calls all the initialization code for all the other modules and provides the while (1) loop to test for application flags. the flags tested by the master include byte level and message level receive flags, transmit status flag to see if all bytes in message have been transmitted, and transmit response flag . if the flag gets set, the test function will call an application function in the related module to act. 9.2.2 16b_timer1.c timer 16b1 on the lpc1114 provides the receive sample timing and is set to interrupt at a rate 16 transmit data rate. the middle five samples of each bit time are used to determine the logic state of the received bit by state of a majority of the samples. 9.2.3 uart.c this is only used for debug. 9.2.4 io.c this configures the i/o of the lpc1114 includi ng setting the functions and direction of the i/o pins. this also configures the rx pin us ed by the plm uart as an external interrupt that detects the high-to-low tr ansition at the beginning of the start bit this module also contains the functions to detect the closure of a command switch and take the appropriate action or sent the corresponding command to the slave. 9.2.5 command.c this is only used for debug. 9.2.6 nvic.c this sets the priority and enables required interrupts in the nested vectored interrupt controller (nvic). the enable interrupts include timers 32b0, 32b1, 16b0, 16b1, and external interrupt eint0.
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 24 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 9.2.7 systick.c the systick timer provides the heartbeat and delay function timing. 9.2.8 32b_timer0.c the 32b0 timer provides the transmit timing for the master transmitter. 9.2.9 i2c.c this contains the driver code for the i 2 c peripheral on the lpc1114. the i 2 c interface is used by the slave to communicate with the pca9632 i 2 c-bus to pwm led driver. the application specific code is contained in the i2c messages.c module described in section 9.2.10 . 9.2.10 i2c messages.c this module contains the functions that in terpret the incoming commands and channel assignments and sends corresponding i 2 c messages to the pca9632. the pca9632 is initialized in the ?group dim mode? where a 190 hz fixed frequency ?group? signal is superimposed with the 6.25 khz individual brightness control signals pwm0, pwm1, pwm2, and pwm3. the ?select? function on th e master sets the outgoing channel number in the plm master transmit frame. this channel number is read by the slave to determine which register on the pca9632 is addressed when it sends out i 2 c commands. the corresponding registers on the pca9632 and a short description are shown in ta b l e 6 . this mode is useful to be able to set the br ightness ?mix? of the different outputs, then increasing or decreasing all outputs at th e same time while still maintaining the same ?mix?. refer to the pca9632 data sheet ( ref. 1 ) for more information. the brightness levels of both the grppwm and pwmx registers are initialized at a mid level of brightness. to get maximum duty cycle from the outputs, increase both group and individual levels via the master ?dim up? and ?dim down? and ?select?. the off/on command from the master results in the slave sending an i 2 c message to the pca9632 to enable or disable all or none of the ledx output drives via the ledout register on the pca9632. the actual levels sent to the grppwm and pwmx registers are incremented via functions that provide a simple piece- wise linear approximation of a logarithmic dimming curve. as the eye sensitivity is logarithmic, providing some approximation of this gives the dim up and dim down commands a more natural response. the dimming curve functions are located in the plm_slave module discussed in section 9.2.11 . 9.2.11 plm_slave.c this handles the message level communications for the plm slave, providing synchronization, rece iving commands, transmitting acknowledgements, and handling error conditions. the receiv ed ?dim up? and ?dim down? comma nds result in pwm values table 6. pca9632 corresponding registers register range of values description grppwm 0 to 15 this is used as a global brightness control allowing the led outputs to be dimmed with the same value pwm0 0 to 63 individual brightness control for pwm0 output pwm1 0 to 63 individual brightness control for pwm1 output pwm2 0 to 63 individual brightness control for pwm2 output pwm3 0 to 63 individual brightness control for pwm3 output
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 25 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 that are incremented or decremented through simple dimming curve functions contained in this module as discussed in the previous section. this module also contains the external interrupt handler used to detect the high-to-low transition of the start bit at the beginning of a bit frame. 9.2.12 plm_uart.c this contains the routines that handle the bi t level synchronization, data transmission, and reception. this uses the timing references fr om the 16b1 and 32b2 timers to implement a soft uart specifically for the interfacing to the tda5051a. 10. demo setup and operation 10.1 demo setup and operation ? zero crossing synchronization 10.1.1 setup requirements, master ? zero crossing synchronization hardware needed (master): ? tda5051a demo board ? 13 v dc power supply ? internally, +5 v and +3.3 v are generated from this using linear regulators. ? 4 mechanical or ?cap sense? switches ? power supply for ?cap s ense? switch assembly ? if ?cap sense? switches are used ? not required when using mechanical switches ? ac line connection ? cabling to mate with headers on demo board for: ? ac line ? dc power ? switch interface ? cap sense supply (as required) 10.1.2 setup requirements, slave ? zero crossing synchronization hardware needed (slave): ? tda5051a demo board ? 13 v dc power supply ? 4 leds with curren t limit resistors ? power supply for led assembly ? ac line connection ? cabling to mate with headers on demo board for: ? ac line ? dc power ? led assembly with current limit resistors ? led power (as required)
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 26 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 10.1.3 demo configuration ? zero crossing synchronization 10.1.3.1 master assemble the hardware pieces described in section 10.1.1 . if the firmware has not been loaded into the lpc1114 on the plm demo boar d master, program the devices with zero crossing master code, v2_09 using one of the programming methods discussed in section 11 ? appendix a ? programming instructions ? . master switch setting: the master does not use the hex switch, however, it is connected to the same pins on the microcontroller as th e control switches. make sure the hex switch on the slave is set to ?0?, the open state, to prevent any conflict with the external switches. hook up the power, ac line, and switches to the tda5051a demo board as shown in figure 13 . fig 13. hook up of power, ac line and switches to tda5051a demo board (master) 002aag480 dc power ac line switches
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 27 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 10.1.3.2 slave assemble the hardware pieces described in section 10.1.2 . if the firmware has not been loaded into the lpc1114 on the plm demo board slave, program the devices with zero crossing slave code, v2_09 using one of the programming methods discussed in section 11 ? appendix a ? programming instructions ? . slave switch setting: the firmware is set up to transmit to slave address ?1?. make sure the hex switch on the slave is set to ?1?. hook up the power, ac line, and leds to the tda5051a demo board as shown in figure 14 . 10.1.4 demo operation ? zero crossing synchronization with both master and slave powered and connected to the line, the hb led should blink on both units. the slave should initia lize with the leds illuminated at about 1 4 of the maximum. when the ?dim up? switch is pres sed, the leds connec ted to the pca9632 outputs will get brighter. when the data is being received by the slave, the ?com_led? will blink. when the ?dim down? switch is pres sed, the leds connec ted to the pca9632 outputs will get dimmer. when this data is be ing received by the slave, the ?com_led? will blink. the on/off switch sends the on/off command to the slave. fig 14. hookup of dc power, ac line and leds to tda5051a high-bay demo board (slave) 002aag481 dc power ac line leds
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 28 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 the ?select? switch will select different dim modes. the default sett ing for the ?select? switch is ?group?. in this mode, a dim up or dim down command will affect all led pwm outputs. there are 16 steps from full on to full off in this mode. pressing this switch once will select pwm output 0. the com_led on the master will blink once when pwm0 is selected. only pwm0 will be affected by a dim up or dim down in this mode. there are 64 steps from on to off in this mode. pr essing the switch again will select pwm1 with 64 steps. the com_led on the master will b link twice when pwm1 is selected. pressing the switch again will select pwm2 with 64 st eps. the com_led on the master will blink three times when pwm2 is selected. pressi ng the switch again will select pwm3 with 64 steps. the com_led on the master will b link four times when pwm3 is selected. pressing the switch again will bring you ba ck to the group mode . the com_led on the master will blink 1 long blink when group is selected. the re lative levels of pwm0-pwm3 are preserved when dimming up or down when returning to group mode. additional details on the group dimming mode can be found in the pca9632 data sheet. 10.1.5 troubleshooting ? zero crossing synchronization in case of problems, the first thing to verify is that the hb_leds on both master and slave are blinking. this means the unit is powered up and the microcontroller is functioning. verify the ac line is connected to both master and slave. without an ac line the tda5051a demo board will not try to communicate since it needs to detect a zero crossing to synchronize transmission and reception. on the master, verify the com_led blinks when pr essing ?select?. if not, verify the switch connections. if everything looks good on the master, observe the slave to see if the com led blinks when a ?dim up? or ?dim down? command is re ceived. this will verify the master is communicating with the slave. if everything looks good up to this poin t, but the dim up and dim down are still not functional, verify the led connections to the tda5051a demo board. if the leds need external power, verify the led power is operational. if still not functional, verify the led0-led3 ou tputs with an oscilloscop e to determine if a pwm signal is present. if the pwm signal is present, the problem is probably bad leds or other problems with the led assembly.
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 29 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 10.2 setup requirements ? start bit (uart style) synchronization 10.2.1 setup requirements, master ? start bit (uart style) synchronization hardware needed (master): ? tda5051a demo board ? 13 v dc power supply ? internally, +5 v and +3.3 v are generated from this using linear regulators. ? 4 mechanical or ?cap sense? switches ? power supply for ?cap s ense? switch assembly ? if ?cap sense? switches are used ? not required when using mechanical switches ? ac or dc line connection ? dc lines may need a small network at each end to provide a controlled impedance to the plm demo board. ? cabling to mate with headers on demo board for: ? ac or dc line and networks ? dc power ? switch interface ? cap sense supply (as required) 10.2.2 setup requirements, slave ? start bit (uart style) synchronization hardware needed (slave): ? tda5051a demo board ? 13 v dc power supply ? 4 leds with curren t limit resistors ? power supply for led assembly ? ac or dc line connection ? cabling to mate with headers on demo board for: ? ac or dc line and networks ? dc power ? led assembly with curr ent limit resistors ? led power (as required)
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 30 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 10.2.3 demo configuration ? start bit (uart style) synchronization 10.2.3.1 master assemble the hardware pieces described in section 10.2.1 . if the firmware has not been loaded into the lpc1114 on the plm demo board master, program the devices with uart style master code, v1_1 using one of the programming methods discussed in section 11 ? appendix a ? programming instructions ? . master switch setting: the master does not use the hex switch, however, it is connected to the same pins on the microcontroller as th e control switches. make sure the hex switch on the slave is set to ?0?, the open state, to prevent any conflict with the external switches. hook up the power, ac line, and switches to the tda5051a demo board as shown in figure 15 . fig 15. hook up of power, ac line and switches to the tda5051a demo board (master) 002aag482 dc power ac or dc line switches
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 31 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 10.2.3.2 slave assemble the hardware pieces described in section 10.2.2 . if the firmware has not been loaded into the lpc1114 on the plm demo board slave, program the devices with uart style slave code, v1_1 using one of the programming methods discussed in section 11 ? appendix a ? programming instructions ? . slave switch setting: the firmware is set up to transmit to sl ave address ?1?, so make sure the hex switch on the slave is set to ?1?. hook up the power, ac line, and leds to the tda5051a demo board as shown in the following: fig 16. hookup of power, ac line and leds to tda5051a demo board (slave) dc power ac or dc line
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 32 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 10.2.4 demo operation ? start bit (uart style) synchronization with both master and slave powered and conn ected to the line, the hb_led should blink on both units. the slave should initia lize with the leds illuminated at about 1 4 of the maximum. when the ?dim up? switch is pre ssed, the leds connected to the pca9632 outputs will get brighter. when the data is being received by the slave, the ?com_led? will blink. when the ?dim down? sw itch is pressed, the leds connected to the pca9632 outputs will get dimmer. when this data is be ing received by the slave, the ?com_led? will blink. the on/off switch sends the on/off command to the slave. the ?select? switch will select different dim modes. the default sett ing for the ?select? switch is ?group?. in this mode, a dim up or dim down command will affect all led pwm outputs. there are 16 steps from full on to full off in this mode. pressing this switch once will select pwm output 0. the com_led on the master will blink once when pwm0 is selected. only pwm0 will be affected by a dim up or dim down in this mode. there are 64 steps from on to off in this mode. pr essing the switch again will select pwm1 with 64 steps. the com_led on the master will b link twice when pwm1 is selected. pressing the switch again will select pwm2 with 64 st eps. the com_led on the master will blink three times when pwm2 is selected. pressi ng the switch again will select pwm3 with 64 steps. the com_led on the master will b link four times when pwm3 is selected. pressing the switch again will bring you ba ck to the group mode . the com_led on the master will blink one long blink when grou p is selected. the relative levels of pwm0-pwm3 are preserved when dimming up or down when returning to group mode. additional details on the group dimming mode can be found in the pca9632 data sheet. remark: when using this to communicate over dc lines it is likely that a simple inductive-resistive network is needed in series at the source and the load to give a low dc resistance to minimize any i2r losses, but provide a known impedance at 125 khz for the tda5051a to communicate. 10.2.5 troubleshooting ? start bit (uart style) synchronization in case of problems, the first thing to verify is that the hb_leds on both master and slave are blinking. this means the unit is powered up and the microcontroller is functioning. verify the connections to the power are complete. on the master, verify the com_led blinks when pr essing ?select?. if not, verify the switch connections. if everything looks good on the master, observe the slave to see if the com_led blinks when a ?dim up? or ?dim down? command is rece ived. this will verify the master is communicating with the slave. if everything looks good up to this poin t, but the dim up and dim down are still not functional, verify the led connections to the tda5051a demo board. if the leds need external power, verify the led power is operational. if still not functional, verify the led0-led3 ou tputs with an oscilloscop e to determine if a pwm signal is present. if the pwm signal is present, the problem is probably bad leds or other problems with the led assembly.
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 33 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 11. appendix a ? programming instructions the tda5051a demo board can be programmed via an rs-232 interface onboard, or via the serial wire debug interfac e available on the lpc1114. 11.1 rs-232 interface a max3232 rs-232 interface is provided on the tda5051a to provide a programming interface to program the device via the isp (in-system programming) ca pability. the rs-232 signals are brought out on connector sv4 with the pin assignments as follows: pin 1 ? ground pin 2 ? receive pin 3 ? transmit pin 4 ? lpc1114 reset to put the device into isp mode, insert a jumper into jp1 (isp_mode) and reset the device by grounding the reset pin and releasing, or cycling the power to provide a power-on reset. the isp configuration is shown in figure 17 . fig 17. isp configuration 002aag484 rs-232 interface isp jumper
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 34 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 a pc utility is then needed to send the program code to th e microcontroller. the utility used is flash magic ( www.nxp.com/redirect/flashmagictool.com ). this is a free download. install the utility and open it up . configure the ut ility as follows: for step 1, the com port is the rs-232 por t assignment for your pc, usually com1. fill in the other entries as shown in figure 18 . for step 2, check the box as shown in figure 18 . for step 3, browse to the hex file provided for programming. in addition to the above set up values, pull down the options menu and select ?advanced options?. the communications and hardware configurations should be set as shown in figure 19 and figure 20 . fig 18. configure flash magic utility 002aag485
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 35 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 to verify flash magic is connected, pull do wn the ?isp? tab and select ?read device signature?. if flash magic returns a signature similar to that shown in figure 21 , then communications is established. fig 19. communications configuration fig 20. hardware configuration 002aag486 002aag487
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 36 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 to complete programming, verify the correct hex file is loaded and press ?start? (step 5 in the flash magic window shown in figure 18 ). fig 21. ?read device signature? result 002aag488
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 37 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 11.2 sw programming interface the board may also be programmed via sw (serial wire). many of the ide vendors support swd programming. the swd cable should be removed after programming to ensure proper operation. the debug conn ection for swd programming is shown in figure 22 . to program via swd, open up keil uvision4, mdk-arm version 4.21 or higher. make sure the correct project is loaded and compiled. the press the ?load? button as shown in figure 23 . fig 22. debug connection for swd programming 002aag489 swdebug connector
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 38 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 fig 23. ?load? button 002aag490 load
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 39 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 12. appendix b ? tda5051a lighting demo board schematic fig 24. tda5051a lighting demo board schematic 019aac665 reset/pio0_0 2 pio0_1/clkout/ct32b0_mat2 3 pio0_2/ssel0/ct16b0_cap0 8 pio0_3 9 pio0_4/scl 10 pio0_5/sda 11 jtag_reset pio0_6/sck0 15 pio0_7/cts 16 pio0_8/miso0/ct16b0_mat0 17 pio0_9/mosi0/ct16b0_mat1 18 swclk/pio0_10/sck0/ct16b0_mat2 19 r/pio0_11/ad0/ct32b0_mat3 21 xtalin 4 xtalout 5 vdd(3v3) 29 vdd(io) 6 vss 33 r/pio1_0/ad1/ct32b1_cap0 22 r/pio1_1/ad2/ct32b1_mat0 23 r/pio1_2/ad3/ct32b1_mat1 24 swdio/pio1_3/ad4/ct32b1_mat2 25 pio1_4/ad5/ct32b1_mat3/wakeup 26 pio1_5/rts/ct32b0_cap0 30 pio1_6/rxd/ct32b0_mat0 31 pio1_7/txd/ct32b0_mat1 32 pio1_8/ct16b1_cap0 7 pio1_9/ct16b1_mat0 12 pio1_10/ad6/ct16b1_mat1 20 pio1_11/ad7 27 pio2_0/dtr 1 pio3_4 13 pio3_5 14 pio3_2 28 bus_u jtag_tms_swdio rx tx lpc1114fhn33 ic2 8 4 2 1 sw crd16rm0sb0sb 0 4 8 c e 2 6 a f 3 7 b 1 5 9 d c2 c1 slave address gnd 1 2 3 4 5 gnd sv2 external switches hb_led com_led +3.3 v +3.3 v r3 220 r4 220 c7 0.1 f gnd +3.3 v c5 0.1 f 1 3 5 7 9 gnd jtag +3.3 v r5 100 k 2 4 6 8 10 jtag_tclk_swclk r7 10 k jtag_reset jtag_tms_swdio mini jtag/swd connector top side +3.3 v r2out 9 r1out 12 t2in 10 t1in 11 c2? 5 c2+ 4 c1? 3 c1+ 1 rx tx c3 0.1 f c4 0.1 f max3232cue ic6 r2in r1in t2out t1out 8 13 7 14 u? u+ 6 2 1 2 3 4 sv4 jtag_reset gnd top side isp_i/f c2 0.1 f c1 0.1 f +3.3 v gnd c11 0.1 f gnd ic6p +3.3 v 15 16 vcc gnd +3.3 v gnd jtag_tclk_swclk plm_zc plm_pd sda scl 1 2 jp1 gnd isp_mode ic1p 2 3 gnd gnd ic1 4 5 vcc +3.3 v 74ahc1g06dck r15 4.7 k +5 v agnd 12 apgnd 9 dgnd 5 scantest 6 osc1 8 osc2 7 datain 1 dataout 2 clkout 4 pd 15 gnd vdda 13 vddap 11 vddd 3 test1 16 rxin 14 txout 10 ic4 tda5051at c14 0.01 f c13 10 f 16 v d1 ptvs7v0s1ur gnd c18 0.01 f +5 v c21 0.1 f gnd c20 100 f c22 2200 pf gnd plm_zc zero cross detector gnd q1 pmbt3904 r10 10 k r9 1 k r12 4.7 k gnd +5 v r1 100 c17 0.1 f, 25 v l2 22 h (rfb0807-220l) 1 2 34 5 6 t1 78250_sipm l1 47 h (rfb0807-470l) c19 47 nf (mpxqs47k) ps 6 5 4 ok1 il250 r2 220 k 1 2 r8 1 m u r6 p593 f1 370-0630-0410 1 1 warning: high voltage gnd l n led0 pin1 led1 pin2 led2 pin3 led3 pin4 ic5 sda scl pin7 pin6 gnd pin5 gnd vcc pin8 +3.3 v pca9632dp r16 1 k r17 1 k sda scl +3.3 v 5 4 3 2 1 gnd j501 5 4 3 2 1 j502 +13 v gnd r11 52 k bus v r13 3.3 k c15 0.1 f gnd in 1 en 3 adj 4 c9 0.1 f r14 22 +13 v gnd gnd 2 out 5 ic7 mic5219bm5 +5 v in 1 en 3 adj 4 gnd gnd 2 out 5 ic3 mic5205-3.3ym5 c16 0.1 f +3.3 v
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 40 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 13. abbreviations 14. references [1] pca9632, 4-bit fm+ i 2 c-bus low power led driver ? nxp semiconductors; product data sheet; www.nxp.com/documents/ data_sheet/pca9632.pdf table 7. abbreviations acronym description adc analog-to-digital converter agc automatic gain control ask amplitude shift keying cl current limiting (resistor) dac digital-to-analog converter i 2 c-bus inter integrated circuit bus i/o input/output ide integrated development environment led light emitting diode nvic nested vectored interrupt controller plm power line modem pwm pulse width modulation rom read only memory ssl solid state lighting swd serial wire debug uart universal asynchronous receiver/transmitter
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 41 of 43 nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 15. legal information 15.1 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. 15.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconducto rs products, and nxp semiconductors accepts no liability for any assistance wi th applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from competent authorities. evaluation products ? this product is provided on an ?as is? and ?with all faults? basis for evaluati on purposes only. nxp semico nductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. the entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. in no event shall nxp semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. notwithstanding any damages that customer might incur for any reason whatsoever (including without limitat ion, all damages referenced above and all direct or general damages), the entire liability of nxp semiconductors, its affiliates and their suppliers and custom er?s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (us$5.00) . the foregoing limitations, exclusions and disclaimers shall apply to the ma ximum extent permitted by applicable law, even if any remedy fails of its essential purpose. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.3 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners.
UM10495 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 2 ? 11 may 2012 42 of 43 continued >> nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 16. contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 plm demo board . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 power line communications . . . . . . . . . . . . . . . 4 2.2 demo application overview. . . . . . . . . . . . . . . . 4 3 hardware requirements. . . . . . . . . . . . . . . . . . . 5 3.1 master hardware configuration . . . . . . . . . . . . . 5 3.2 slave configuration . . . . . . . . . . . . . . . . . . . . . . 5 4 master hardware description ? tda5051a demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.1 tda5051a demo board ? general . . . . . . . . . 5 4.2 tda5051a demo board ? i/o, master configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2.1 onboard visual indicators . . . . . . . . . . . . . . . . . 6 4.2.2 external switch interface. . . . . . . . . . . . . . . . . . 6 4.2.3 demo board connections ? master configuration . . . . . . . . . . . . . . . . . . . . . 8 5 tda5051a demo board ? slave configuration . . . . . . . . . . . . . . . . . . . . . . 9 5.1 tda5051a demo board ? i/o, slave configuration . . . . . . . . . . . . . . . . . . 10 5.1.1 onboard visual indicators ? slave configuration . . . . . . . . . . . . . . . . . . . . . 10 5.1.2 external led interface . . . . . . . . . . . . . . . . . . 10 5.1.3 demo board connections ? slave configuration . . . . . . . . . . . . . . . . . . . . . 11 6 protocol requirements. . . . . . . . . . . . . . . . . . . 12 6.1 bit frame protocol considerations ? zero crossing synchronization . . . . . . . . . . . . 12 6.2 bit frame protocol considerations ? start bit (uart style) synchronization . . . . . . 12 7 protocol specification . . . . . . . . . . . . . . . . . . . 13 7.1 protocol specification ? zero crossing synchronization . . . . . . . . . . . . 13 7.1.1 bit level protocol ? zero crossing synchronization . . . . . . . . . . . . 13 7.1.2 message level protocol . . . . . . . . . . . . . . . . . . 14 7.2 protocol specification ? start bit (uart style) synchronization . . . . . . 15 7.2.1 bit level protocol ? start bit (uart style) synchronization . . . . . . 15 8 master firmware overview . . . . . . . . . . . . . . . . 16 8.1 master firmware implementation ? zero crossing synchronization . . . . . . . . . . . . 17 8.1.1 main_loop.c . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.1.2 16b_timer1.c . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.1.3 uart.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.1.4 io.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.1.5 command.c . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.1.6 nvic.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1.7 systick.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1.8 32b_timer0.c . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1.9 plm_master.c . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1.10 32b_timer1.c . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1.11 timer16b_0.c . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1.12 plm_uart.c . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.2 master firmware implementation ? start bit (uart style) synchronization . . . . . . 19 8.2.1 main_loop.c . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2.2 16b_timer1.c . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2.3 uart.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2.4 io.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2.5 command.c . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2.6 nvic.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2.7 systick.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2.8 32b_timer0.c . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2.9 plm_master.c . . . . . . . . . . . . . . . . . . . . . . . . 20 8.2.10 32b_timer1.c . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.2.11 timer16b_0.c . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.2.12 plm_uart.c . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 slave firmware description . . . . . . . . . . . . . . 20 9.1 slave firmware description ? zero crossing synchronization . . . . . . . . . . . . 21 9.1.1 main_loop.c . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1.2 16b_timer1.c . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1.3 uart.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1.4 io.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1.5 command.c . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1.6 nvic.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1.7 systick.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1.8 32b_timer0.c . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1.9 i2c.c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1.10 i2c messages.c . . . . . . . . . . . . . . . . . . . . . . . 22 9.1.11 plm_slave.c . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1.12 32b_timer1.c . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1.13 timer16b_0.c . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.1.14 plm_uart.c . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2 slave firmware description ? start bit (uart style) synchronization . . . . . . 23 9.2.1 main_loop.c . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2.2 16b_timer1.c . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2.3 uart.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2.4 io.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2.5 command.c . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2.6 nvic.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
nxp semiconductors UM10495 tda5051a lighting master-slave demo board om13314 ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 11 may 2012 document identifier: UM10495 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 9.2.7 systick.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.8 32b_timer0.c . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.9 i2c.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.10 i2c messages.c . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.11 plm_slave.c . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.12 plm_uart.c . . . . . . . . . . . . . . . . . . . . . . . . . 25 10 demo setup and operation . . . . . . . . . . . . . . . 25 10.1 demo setup and operation ? zero crossing synchronization . . . . . . . . . . . . 25 10.1.1 setup requirements, master ? zero crossing synchronization . . . . . . . . . . . . 25 10.1.2 setup requirements, slave ? zero crossing synchronization . . . . . . . . . . . . 25 10.1.3 demo configuration ? zero crossing synchronization . . . . . . . . . . . . 26 10.1.3.1 master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.1.3.2 slave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.1.4 demo operation ? zero crossing synchronization . . . . . . . . . . . . 27 10.1.5 troubleshooting ? zero crossing synchronization . . . . . . . . . . . . 28 10.2 setup requirements ? start bit (uart style) synchronization . . . . . . 29 10.2.1 setup requirements, master ? start bit (uart style) synchronization . . . . . . 29 10.2.2 setup requirements, slave ? start bit (uart style) synchronization . . . . . . 29 10.2.3 demo configuration ? start bit (uart style) synchronization . . . . . . 30 10.2.3.1 master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.2.3.2 slave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.2.4 demo operation ? start bit (uart style) synchronization . . . . . . 32 10.2.5 troubleshooting ? start bit (uart style) synchronization . . . . . . 32 11 appendix a ? programming instructions . . 33 11.1 rs-232 interface. . . . . . . . . . . . . . . . . . . . . . . 33 11.2 sw programming interface . . . . . . . . . . . . . . . 37 12 appendix b ? tda5051a lighting demo board schematic . . . . . . . . . . . . . . . . . . 39 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 40 14 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 41 15.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 15.2 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 15.3 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 41 16 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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